GMII SPECIFICATION PDF

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The KSZMNX offers the industry-standard GMII/MII Media Independent Interface (GMII) is compliant to the IEEE Specification. Dave Fifield [email protected] GMII Electrical Specification IEEE Interim Meeting, San Diego, January N. Interface) for connection to GMII/MII MACs in Gigabit . Clarified power cycling specification to have all supply voltages to the KSZMNX.

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There are 32 addresses, each containing 16 bits. Retrieved from spedification https: The receive clock is recovered from the incoming signal during frame reception. Archived from the original on Ethernet family of local area network technologies. By using this site, you agree to the Terms of Use and Privacy Policy. The MAC may omit the signal if it has no use for this functionality, in which case the signal should be tied low for the PHY.

Source-synchronous clocking is used: Retrieved 20 April On the other hand, newer devices may support 2. The management interface controls the behavior of the PHY.

More recently, raising transmit error outside frame transmission is used to indicate the transmit data lines are being used for special-purpose signalling.

As such it consists of a preamble, start frame delimiter, Ethernet headers, protocol specific data and a cyclic redundancy check CRC.

This interface requires 9 signals, versus MII’s Some of the preamble nibbles may be lost. Received clock signal recovered from incoming received data. At power up, speciification autonegotiationthe PHY usually adapts to whatever it is connected to unless settings are altered via the MDIO interface.

The RMII signals are treated as lumped signals rather than transmission lines; no termination or controlled impedance is necessary; output drive and thus slew rates need to be as slow as possible rise times from 1—5 ns to permit this.

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Current revisions of IEEE Typically used for on-chip connections; in chip-to-chip usage mostly replaced by XAUI. There is no signal which defines whether the interface is in full or half duplex mode, but both the MAC and the PHY need to agree.

Media-independent interface

It contains a bitmask with the following meaning: This page was last edited on 19 November spwcification, at Input high threshold is 2. Given trends in the semiconductor industry and the fact that both ICs are usually on the same board, lack of 5 V tolerance is probably very common, and chips that actually drive 5 V are probably even rarer.

The transmit enable signal is held high during frame transmission and low when the transmitter is idle. It is not to be confused with RM2. TTL signal levels are used for 5 V or 3. The first 16 addresses have a defined usage, [7] while the others are device specific. Transmit error may be raised for one or more clock periods during specifiation transmission to request the PHY to deliberately corrupt the frame in some visible way that precludes it from being received as valid.

At least the standard says the signals need not be treated as transmission lines. If a collision is detected, COL also goes high while the collision persists. This requires the PCB to be designed to add a 1.

The original MII transfers network data using 4-bit nibbles in each direction 4 transmit data bits, 4 receive data bits. Ethernet Computer buses Serial buses. For this reason, the reduced media independent interface was developed.

Media-independent interface – Wikipedia

These registers can be used to configure the device say “only gigabit, full duplex”, or “only full duplex” or can be used to determine the current operating mode. Transmit and receive path each use one differential pair for data and another differential pair for clock.

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The specification states that inputs should be 5 V tolerant, however, some popular chips with RMII interfaces are not 5 V tolerant. The receiver clock is much simpler, with only one clock, which is recovered from the incoming data. This may be used to abort a frame when some problem is detected after transmission has already started. Carrier sense is high when transmitting, receiving, or the medium is otherwise sensed specidication being in use.

Reference clock may be an input on both devices from an external clock source, or may be driven from the MAC to the PHY.

This arrangement allows the MAC to operate without having to be aware of the link speed. However, at 1 ns edge rates a trace longer than about 2.

When no clock can be recovered i. The media-independent interface MII was originally defined as a standard interface to connect a Fast Ethernet i.

The standard MII features a small set of registers: Drivers should be able to drive 25 pF of capacitance which allows for PCB traces up to 0. Views Read Edit View history. Data is sampled on the rising edge only i. Being media independent means that different types of PHY devices for connecting to different media i. Four things were changed compared to the MII standard to achieve this:.